1. Field of the Invention
The present invention relates to a wafer prober that automatically brings probes into contact with pads of multiple chips formed on a wafer and tests chip characteristics.
2. Description of the Related Art
Generally, in the semiconductor manufacturing process, devices and conductive patterns that constitute a plurality of chips 51 are formed on the surface of, typically disk-shaped, wafer 50 as shown in FIG. 1. Wafer 50 with devices and conductive patterns formed thereon is then diced along the predetermined scribe lines so as to produce individual, typically square-shaped, chips 51 to be the products. In this semiconductor manufacturing process, it has been known as a practice to measure the characteristics of chips 51 formed on wafer 50 before chips 51 are separated, by using a wafer prober so as to examine whether any defective chips 51 are present.
As a wafer prober, a configuration has been known which uses a probe card having a multiple number of probes formed in a predetermined planar pattern so that they will come into contact with a multiple number of bonding pads, typically made of aluminum and formed on chips 51. This wafer prober performs test of each chip 51 by precisely positioning its probe card relative to wafer 50 so that the probes come into contact with the bonding pads of each chip 51 at predetermined positions and by measuring electric characteristics between the bonding pads.
Thereafter, the wafer prober is moved relative to wafer 50 in order to examine different chips 51 on wafer 50 because the probe card is generally smaller than wafer 50. Thus, multiple shots for measurement are performed for single wafer 50. In this process, if the probes touch the same location on the same bonding pad several times due to multiple shots for measurement, there is a risk that the bonding pad might be badly scratched or might be peeled off in some cases, causing the problem that chip 51 cannot be correctly connected to the mounting substrate or the like.
To avoid this, in conventional wafer probers, a test is performed by varying the placement of the probe card relative to wafer 50 from one shot to another so that no probes will touch the same bonding pad. In other words, the placement of the probe card relative to wafer 50 at the time of each shot for measurement is performed in accordance with a placement pattern (a wafer shot pattern or a wafer shot map) in which the probe card is positioned relative to wafer 50 at the time of multiple shots for measurement, so that one area on the wafer covered by the probe card at the time of one shot does not overlap with another area covered thereby at the time of another shot. The square frame lines in FIG. 1 show one example of this wafer shot pattern. That is, each frame indicates the placement position of the probe card at the time of each measurement is taken.
In the example shown in FIG. 1, when the wafer probe is positioned over the area near the periphery of wafer 50, only a relatively low number of chips 51 can be examined by one shot for measurement. Moreover, in some cases depending on the sizes of wafer 50 and probe card 52, it could be necessary to perform one shot for measurement for a still lower number of chips 51. In this way, there are cases where examination throughput becomes inefficient due to low flexibility of the wafer shot pattern.
On the other hand, Japanese Patent Application Laid-open 60-117638 discloses a wafer manufacturing process in which a multiple number of functional tests are implemented under different conditions such as normal temperature, high temperature, low temperature and the like. In this case, in order to avoid an adverse effect due to contacts of the probe against the same location of any bonding pad, a multiple number of probe cards are used, which are differentiated from each other in a pattern of probes so that each pattern of probes comes into contact with bonding pads at different positions from those of another pattern.